11. JTAG Interface Operation

11.4 Boundary Scan Register

The boundary scan data register is selected by loading 0000 into the instruction register. The Shift-DR, Update-DR, and Capture-DR states of the TAP controller are used to operate the boundary scan register according to the IEEE 1149.1 standard specifications.

The boundary scan register provides serial access to each of the processor interface pins, as shown in Figure 11-1. Hence, the boundary scan register can be used to load and observe specific logic values on the processor pins.

Figure 11-1 JTAG Boundary Scan Cells

The main application of the boundary scan register is board-level interconnect testing.

The use of the boundary scan register for applying data to and capturing data from the internal microprocessor circuitry is not supported.

The boundary scan register list for rev 1.2 of the fab is given in Table 11-2. The TriState signal will be eliminated from the BSR in rev 2.0 of the fab, and beyond.

An additional bit is provided in the boundary scan register to control the direction of bidirectional pins. As it is loaded through JTDI, this bit is the first bit in the boundary scan chain. The logic value of this bit is latched during the Update-DR state, and sets the direction of all bidirectional pins as follows:

The value is set to 0 during reset, setting all bidirectional pins to input prior to any boundary scan operations.

Table 11-2 Boundary Scan Register Pinlist, rev 1.2

Table 11-2 (cont.) Boundary Scan Register Pinlist, rev 1.2